Resistive memory elements in an antiserial circuit, composed of two resistive memory cells, according to German patent 10 2009 023 153 combine the fast access time of DRAMs with the non-volatility of flash memories and are therefore suitable for combining random access memories and bulk memories in computer technology. Digital information is encoded in these in two stable states, these being 0 and 1, in each of which the memory element has a high overall resistance. In large arrays composed of many memory elements, this minimizes parasitic currents that are superimposed on the signal that is created during read-out of individual memory elements.
So as to be able to distinguish the two states having a large signal deviation from each other during read-out, the memory element is activated using a read voltage so that this is transferred to a ON state having low overall resistance, proceeding from the state 1, but not proceeding from the state 0. The disadvantage is that this readout is destructive, which is to say the originally present 1 is lost and must be re-written to the memory element. This consumes time and energy and further shortens the service life of the memory element, since the active material degrades by a small amount with every write process, and memories are generally read much more frequently than written.
From German patent 10 2011 012 738 it is known to design resistive memory elements such that they nave differing capacitances in the states 0 and 1, and to detect this difference in a non-destructive manner during read-out. The drawback is that this advantage is achieved at the expense of the usable signal deviation decreasing very rapidly in an array that is composed of many memory elements as the array size increases.
It is the object of the invention to provide a method for reading out a memory cell, which can be used to solve the tradeoff between non-destructive read-out and a large signal deviation in an array that is composed of many memory elements.